A cost-efficient hardware architecture of deblocking filter in HEVC
VCIP, pp. 209-212, 2014.
This paper presents a hardware architecture of deblocking filter (DBF) for High Efficiency Video Coding (HEVC) by jointly considering system throughput and hardware cost. A hybrid pipeline with two processing levels is adopted to improve system performance. With the hybrid pipeline, only one 1-D filter and single-port on-chip SRAM are use...更多
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