An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms
NOCS, pp. 17-24, 2014.
In this work, we propose a new Network-on-Chip (NoC) architecture for implementing the hierarchical parallel genetic algorithm (HPGA) on a multi-core System-on-Chip (SoC) platform. We first derive the speedup metric of an NoC architecture which directly maps the HPGA onto NoC in order to identify the main sources of performance bottleneck...More
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