10 Gb/s adaptive receive-side near-end and far-end crosstalk cancellation circuitry

Circuits and Systems(2014)

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摘要
As serial I/O data rates scale above 10 Gb/s, crosstalk between neighboring channels degrades system bit-error rate (BER) performance. This paper presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an on-die sign-sign least-mean square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. A prototype fabricated in a general purpose 65-nm CMOS process includes the adaptive NEXT and FEXT circuitry, along with a continuous-time linear equalizer (CTLE) to compensate for frequency-dependent channel loss. Enabling the crosstalk cancellation circuitry while operating at 10 Gb/s over coupled 4-in FR4 transmission line channels with NEXT and FEXT aggressors opens a previously closed eye and allows for a 0.2 UI timing margin at a BER = 10-9. Total power including the NEXT/FEXT crosstalk cancellation circuitry, CTLE, and high-speed output buffer is 34.6 mW, and the core circuit area occupies 0.3 mm2.
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关键词
cmos digital integrated circuits,fir filters,iir filters,band-pass filters,continuous time filters,crosstalk,least mean squares methods,ber,ctle,fir filter taps,next-fext cancellation,ss-lms,ui timing margin,adaptive receive-side near-end crosstalk cancellation circuitry,aggressor signal coupling,bit rate 10 gbit/s,continuous-time band-pass filter iir tap,continuous-time linear equalizer,coupled 4-in fr4 transmission line channels,differentiator circuit,far-end crosstalk cancellation circuitry,filter tap coefficients,frequency-dependent channel loss compensation,general purpose cmos process,high-speed output buffer,neighboring channels,on-die sign-sign least-mean square adaptation engine,power 34.6 mw,power-detection-based adaptation loop,process-voltage and temperature variations,serial i/o data rates,size 65 nm,system bit-error rate performance
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