A 1–100Mb/s 0.5–9.9mW LDPC convolutional code decoder for body area network

Chih-Lung Chen,Sheng-Jhan Wu,Hsie-Chia Chang,Chen-Yi Lee

A-SSCC（2014）

引用 5|浏览6

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摘要

A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1~100Mb/s with power consumption of 0.5~9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.

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关键词

cmos integrated circuits,zigbee,body area networks,convolutional codes,forward error correction,low-power electronics,parity check codes,power consumption,cmos technology,fec candidate,ieee 802.15.4g,ieee 802.15.6,viterbi decoder,bit rate 1 mbit/s to 100 mbit/s,body area network,error correcting performance,low power ldpc convolutional code decoder,power 0.5 mw to 9.9 mw,shift-shared memory architecture,silicon area,size 90 nm,supply voltage,voltage 0.6 v,decoding

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