High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

Jonghae Kim,J O Plouchart,N Zamdmer,Neric Fong,Lianghung Lu,Yue Tan,Keith A Jenkins,M Sherony,Robert A Groves,Mahender Kumar,Arun Kumar Ray

Radio Frequency Integrated Circuits（2003）

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摘要

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 μm SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-Turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH/μm2 is obtained for a 42 nH MTS (Multi-Turn, multiple metal layers in Series) inductor.

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关键词

cmos integrated circuits,single-turn multiple metal levels in parallel,5 ghz,integrated circuit technology,high-q inductors,3d on-chip inductors,mts inductor,si,copper,monolithic rf circuit applications,rfic,cu,metal stacking scheme,soi cmos technology,radiofrequency integrated circuits,stp inductor,equivalent circuits,silicon-on-insulator,three-dimensional on-chip inductors,three-dimensional inductors,high-performance on-chip inductors,high-inductance-density inductors,q-factor,high-resistivity substrate,cu metal layers,0.12 micron,multi-turn multiple metal layers in series,thin film inductors,three dimensional,silicon on insulator,chip

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