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Sequential logic optimization by redundancy addition and removal

Santa Clara, CA, USA, pp.310-315, (1993)

Cited by: 101|Views7
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Abstract

This paper presents a method of multi-level logic optimization for combinational and synchronous sequential logic. The circuits are optimized through iterative addition and removal of redundancies. Among the large number of possible connections that can be added, the proposed method can efficiently identify those connections that would cr...More

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