Domain specific reconfigurable fabric targeting Viterbi algorithm
FPT（2004）
摘要
This work presents a novel embedded reconfigurable fabric targeting efficient implementation of the Viterbi decoder within a system-on-chip device. The proposed reconfigurable fabric can support constraint lengths ranging from 3 to 9, and code rates in the range 1/2-1/3.Our results demonstrate that this novel architecture has superior throughput and power consumption characteristics when compared to generic DSPs and FPGAs respectively.
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关键词
Viterbi decoding,digital signal processing chips,embedded systems,field programmable gate arrays,reconfigurable architectures,system-on-chip,DSP,FPGA,Viterbi algorithm,Viterbi decoder,domain specific reconfigurable fabric targeting,embedded reconfigurable fabric targeting,power consumption,system-on-chip device
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