A practical cut-based physical retiming algorithm for field programmable gate arrays
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific(2005)
摘要
This paper presents a heuristic cut-based retiming algorithm for FPGA designs. It handles complex retiming constraints including timing, architectural and structural constraints; improves retimeability by incorporating logic resynthesis; and efficiently integrates with incremental placement. Thus, the algorithm improves timing compliance by allowing groups of registers to be rapidly retimed across blocks of combinational logic in the physical domain without violating any complex constraints. Experiments have shown that this algorithm can improve the performance of FPGA designs by 16% on average, while achieving a 61.7% speedup in terms of runtime compared with classic retiming algorithms.
更多查看译文
关键词
algorithm theory,combinational circuits,field programmable gate arrays,heuristic programming,logic design,network synthesis,FPGA designs,combinational logic,cut-based retiming algorithm,field programmable gate arrays,heuristic retiming algorithm,logic resynthesis,physical retiming algorithm,practical retiming algorithm
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络