Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization
San Diego, CA(2006)
摘要
To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm2. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process
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关键词
assembling,copper alloys,eutectic alloys,fine-pitch technology,flip-chip devices,integrated circuit interconnections,lead alloys,metallisation,solders,system-in-package,tin alloys,200 mm,3d silicon integration,50 micron,ausn,cusn,pb-free microjoints,snpb,assembly process,electroplating method,eutectic solders,fine pitch interconnection,flip-chip interconnections,solder bumps,solder compositions,solder microjoints,stack plating,system-on-package,under bump metallization,flip chip,chip,system in package,assembly,metallization
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