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Powering networks on chips

ISSS, pp.33-38, (2002)

Cited by: 272|Views15
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Abstract

We consider systems on chips that can be designed and produced in five to ten years from today, with gate lengths in the range 50-100 nm. We address the distinguishing features of a design methodology that aims at achieving reliable designs under the limitations of the interconnect technology. Specifically, we consider energy consumption ...More

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