A 32nm Logic Technology Featuring 2(Nd)-Generation High-K Plus Metal-Gate Transistors, Enhanced Channel Strain And 0.171 Mu M(2) Sram Cell Size In A 291mb Array

A 32nm generation logic technology is described incorporating 2(nd)-generation high-k + metal-gate technology, 193nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 angstrom EOT high-k gate dielectric, dual band-edge workfunction metal gates, and 4(th)-generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. Process yield, performance and reliability are demonstrated on a 291 Mbit SRAM test vehicle, with 0.171 mu m(2) cell size, containing >1.9 billion transistors.