Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities

V Kumar,Rohit Sharma,Jikai Chen,A S Kapoor,Rizwan Bashirullah,Paul A Kohl,Azad Naeemi

Interconnect Technology Conference（2012）

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摘要

In this paper we present a compact model for analysis of 3D chip-to-chip interconnect pathways consisting of planar transmission lines, vias, package and pin discontinuities. The model accurately captures signal losses for a wide frequency spectrum with very small error when compared with HSPICE circuit simulations. The interconnect pathway is optimized for maximum bandwidth density and minimum energy-per-bit highlighting the performance improvement obtained using low-k, air-clad planar interconnects over conventional substrate materials.

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关键词

spice,semiconductor device metallisation,three-dimensional integrated circuits,transmission lines,3d chip-to-chip interconnect pathways,hspice circuit simulations,air-clad planar interconnects,compact modeling,conventional substrate materials,maximum bandwidth density,minimum energy-per-bit,performance optimization,pin discontinuities,planar transmission lines,signal losses,wide frequency spectrum,chip-to-chip interconnects,tsv,modeling and optimization and low-k,optimization,atmospheric modeling,bandwidth,frequency response

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