Fpga Based If Digital Receiver For The Parsax - Polarimetric Agile Radar

An FPGA-based digital receiver has been developed to perform real-time processing for the PARSAX radar. It is a fully polarimetric FMCW radar with dual-orthogonal sounding signals, which has the possibility to measure all elements of the radar targets polarization scattering matrix simultaneously, in one sweep. This paper presents the design principles including the range profile interpretation, optimal parameters selection and processing gain analysis. A novel parallel deramping processing architecture suitable for FPGA implementation is introduced; the overall digital de-ramping processing has been implemented in one chip of FPGA and verified by experimental results.