A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Yasuyuki Hiraku,Isamu Hayashi,Hayun Chung,Tadahiro Kuroda,Hiroki Ishikuro

Solid State Circuits Conference（2012）

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摘要

This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μW at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/MHz. The core area is 0.037mm2.

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关键词

cmos digital integrated circuits,vhf circuits,digital phase locked loops,integrated circuit design,low-power electronics,radiofrequency integrated circuits,radiofrequency oscillators,time-digital conversion,8-phase digitally controlled ring oscillator,cmos technology,tdc,delay-line,frequency 10 mhz to 100 mhz,low- power all-digital pll,power 45.5 muw,power consumption,power scalable ad-pll,size 40 nm,time-to-digital converter,ultralow-voltage all-digital pll,voltage 0.5 v,low power electronics

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