A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration
Solid-State Circuits Conference(2013)
摘要
A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a low-resolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every clock save two decision cycles from every SAR ADC channel, resulting in a reduced number of time interleaving channels with a total 27% energy saving compared with the energy consumption of a conventional TI SAR ADC. A prototype 6 b 2 GS/s ADC in a 45 nm CMOS consumes 14.4 mW under a 1.2 V supply and achieves 5.2 ENOBNyq with a background offset calibration.
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关键词
cmos integrated circuits,analogue-digital conversion,background offset calibration,decision cycles,energy consumption,flash-assisted time-interleaved sar adc,low-resolution flash adc,power 14.4 mw,power-efficient technique,size 45 nm,speed-enhancing technique,time interleaving channels,voltage 1.2 v,word length 6 bit
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