Reliability of barrier engineered charge trapping devices for sub-30nm NAND flash
Electron Devices Meeting(2009)
摘要
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can improve the erase characteristics, but the high electric field for electron de-trapping degrades reliability. Barrier engineering improves reliability by allowing hole erasing instead of high-field detrapping. In extreme scaling to < 20nm nodes, few-electron statistical fluctuation issues and random telegraph noise (RTN) are concerns but CT devices are still quite robust. TFT CT devices are also well suited for 3D scaling.
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关键词
nand circuits,flash memories,high-k dielectric thin films,random noise,reliability,ispp programming efficiency,nand flash memory,barrier engineered charge trapping devices,edge effects,high-k dielectric,high-field detrapping,hole erasing,metal gate,random telegraph noise,capacitors,electric field,high k dielectric,tunneling,programming,edge effect,logic gates
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