3D 65nm CMOS with 320°C microwave dopant activation
Electron Devices Meeting(2009)
摘要
For the first time, CMOS TFTs of 65 nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
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关键词
cmos integrated circuits,mosfet,microwave devices,nanostructured materials,semiconductor doping,semiconductor junctions,thin film transistors,3d-ics fabrication,cmos tft,channel length,low temperature microwave anneal,microwave dopant activation technique,n-mos tft,nanometer-scale transistors,p-mos tft,poly-si gate electrode,size 65 nm,source/drain junctions,temperature 320 c,silicon,logic gates,annealing
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