A 0.33-V, 500-kHz, 3.94- 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
IEEE Transactions on Circuits and Systems Ii-express Briefs(2013)
摘要
This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 × 385 μm2 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 °C. The measured total power consumption is 3.94 μW at 0.33 V, 500 kHz, and 25 °C .
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关键词
CMOS memory circuits,SRAM chips,integrated circuit testing,CMOS technology,RPBL,SRAM compiler qualification patterns,boosting efficiency,frequency 220 MHz,frequency 500 kHz,memory size 72 KByte,negative bit-line write-assist,power 3.94 muW,read access performance improvement,ripple bit-line structure,ripple-initiated NBL write-assist scheme,size 40 nm,temperature 25 degC,ultra-low-power 9T subthreshold SRAM,voltage 0.33 V,voltage 1.1 V,voltage 1.5 V,9T SRAM cell,Negative bit-line (NBL),ripple bit-line (RPBL),subthreshold static random-access memory (SRAM),ultra-low voltage
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