Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

Solid-State and Integrated Circuit Technology, 2012, Pages 1-4.

Cited by: 8|Bibtex|Views6|DOI:https://doi.org/10.1109/ICSICT.2012.6466681
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Abstract:

This paper provides an overview of 3D NAND Flash memory architecture and a comprehensive study on various array decoding methods of vertical gate (VG) NAND Flash. A certain memory density may be achieved by any array architecture but with different numbers of stacking layers. A smaller pitch allows the achieving of high density at reasona...More

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