Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device
Electron Devices Meeting, 2012, Pages 26.7.1-26.7.4.
nand circuitsflash memoriesgrain boundariesinterface statestechnology cad (electronics)More(25+)
The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface sta...More
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