A 128-Channel Time-To-Digital Converter (Tdc) Inside A Virtex-5 Fpga On The Gandalf Module
JOURNAL OF INSTRUMENTATION(2012)
摘要
The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine cards. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In contrast to common TDC concepts, the input signal is sampled by 16 equidistant phase-shifted clocks. A particular challenge of the design is the minimum skew routing of the input signals to the sampling flip-flops. We present measurement results for the differential nonlinearity and the time resolution of the TDC readout system.
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关键词
Digital signal processing (DSP), Trigger concepts and systems (hardware and software), Front-end electronics for detector readout, Digital electronic circuits
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