Effective Half-Pel Motion Compensation And Estimation Scheme For Digital Video

Half-pel motion compensation, unlike its full-pel counterpart, requires the availability of up to four pixels from the reference picture to generate each compensated pixel. To compensate a 16x16 macroblock, a 17x17 array of pixels is needed. The number of memory access cycles necessary to process a macroblock, if half-pel motion compensation is employed, is greater than the number otherwise needed by 33, or 13% of the macroblock size. In some motion prediction modes, two 17x9 pixel arrays are used, and the number of additional cycles increases to 50, or 20% of the macroblock size. This affects the timing requirements for digital video decoding. In particular, a clock frequency higher than the pixel rate is required, as is buffering for pixel data to convert between the two rates.This paper considers the above problem and presents a method of reference picture memory access that eliminates the additional processing time required for half-pel motion compensation. It uses a memory partition and organization strategy, combined with a very simple address and data path architecture, in which the pixel data needed for each half-pel interpolation is stored in such a manner that they are simultaneously available in one memory access. A consequence of this is that the pixel clock may be used for MPEG decoding of half-pel motion-coded images without additional data buffering and without increase in reference picture memory size. This method also has implications for half-pel motion estimation, and may prove particularly effective if memory and logic are integrated onto custom devices designed specifically for motion compensation and estimation.