An Effective SPFD-based Rewiring Scheme for FPGA Performance Improvement

In this work, we implement a new rewiring based flow for FPGA performance improvement in post layout design stage. The rewiring engine is based on SPFD techniques, which is demonstrated to be suitable to work on LUT-based FPGA circuit. The rewiring engine is coupled with the routing stage of VPR, which is currently the most powerful academic CAD tool for FPGA design. While comparing with the already high quality timing results provided by VPR, our new flow can further reduce the delay of the critical path by 11.72% averagely without affecting the original placement or increasing the circuit area. We also compared the results of SPFD-based rewiring with ATPG-based rewiring, which is another most commonly used rewiring technique for FPGA delay optimization. Experiments demonstrate that on LUT-based FPGAs, the SPFD-based is more powerful than the ATPG-based rewiring scheme in finding useful alternative wires to replace target wires for delay improvement, under comparable CPU time.