Simulation Of Gate Lag And Current Collapse In Gan Heterojunction Field Effect Transistors

We present results from numerical simulations of the current collapse phenomenon in GaN Heterostructure Field Effect Transistors. Gate lag simulation results show that current collapse can be explained by an enhanced trapping under the gate edges. Hot electrons play an instrumental role in the collapse mechanism. The simulation results also linked collapse with electrons spreading into the substrate, and confirmed that better electron localization, as in a Double Heterostructure Field Effect Transistor, can dramatically reduce current collapse.