Impact of SMT-induced Edge Dislocation Positions to NFET Performance
2015 73rd Annual Device Research Conference (DRC)(2015)
摘要
This work highlights the impact of SMT-induced edge-dislocation positions in nFET device design. Based on experimental results and atomic transport simulation, dislocations with reduced proximity and depth would increase the amount of SFs and TDs which induce high parasitic resistance and high I boff leakage current together. Trade-off among strained mobility, parasitic resistance and I boff should be made for advanced device design.
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关键词
SMT-induced edge dislocation positions,NFET performance,nFET device design,atomic transport simulation,dislocations,leakage current,strained mobility,parasitic resistance,stress memorization technique
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