Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

shuonan hung
shuonan hung
shihlin huang
shihlin huang
tzung shen chen
tzung shen chen
wenwei yeh
wenwei yeh

2012.

Cited by: 9|Bibtex|Views21|DOI:https://doi.org/10.1109/IEDM.2012.6479015
Other Links: academic.microsoft.com
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