A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)Markchihping chen[0]hangting lue[0]kuopin chang[0]yihsuan hsiao[0]chihchang hsieh[0]shihhung chen[0]yenhao shih[0]kuangyeu hsieh[0]tahone yang[0]kuangchao chen[0]chihyuan lu[0]2012.Cited by: 20|Bibtex|Views17|DOI:https://doi.org/10.1109/VLSIT.2012.6242476Other Links: academic.microsoft.comKeywords: decodinglayoutlogic gatesthin film transistorsvery large scale integrationCode: Data: Full Text (Upload PDF)PPT (Upload PPT)CitedUpload PPTYour rating :0 TagsCommentsSubmit
