Wafer-scale Cu plating uniformity on thin Cu seed layers

The wafer scale plating uniformity with thin Cu seed layer was studied. Plating experiments were performed on 300mm diameter wafers with 4nm, 5nm and 10nm thin Cu seed layers. The plating current distribution can be very nonuniform due to the high substrate resistance. In the case of extremely thin seed layer, the corrosion of Cu due to dissolved oxygen becomes significant. It may lead to exposed barrier layer near the wafer center. A modeling methodology was developed to study the Cu plating uniformity on the wafer scale. Simulation result matches well with experimental measurement and theoretical prediction. The plating uniformity and seed layer corrosion were studied for various seed layer thicknesses using the proposed modeling approach.