Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

IEEE Electron Device Letters, pp. 1461-1463, 2010.

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Abstract:

In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10 000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of...More

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