Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation
IEEE Electron Device Letters, pp. 1015-1017, 2015.
Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading ...More
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