Design of New Low Leakage Power Domino XOR Circuit

In this paper, a new XOR gate is proposed. Proposed circuit adopts mixed N-type and P-type transistors in the pull down network and current mirror at the footer transistor. This topology reduces leakage power consumption. Simulation parameters are measured at 25°C and 110°C. Proposed circuit reduces leakage power consumption up to 51.7% at 25°C and 56% at 110°C as compared to standard N-type domino XOR gate. Similarly, proposed circuit reduces leakage power consumption up to 47.28% at 25°C and 51.1% at 110°C as compared to standard P-type domino XOR gate.