A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS

An SRAM macro, implemented in a 65nm CMOS process, uses a dual supply to maximize density while enabling the use of low voltage for the processor core. Measurements of a 256kb block show 4.2GHz operation using 29mW from 1.2V at 85degC, with core logic operating down to 0.7V and a sleep biasing scheme that autonomously compensates for PVT and aging