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A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.

Jiangfeng Wu,Giuseppe Cusmai,Acer Wei-Te Chou,Tao Wang,Bo Shen,Vijayaramalingam Periasamy,Ming-Hung Hsieh,Chun-Ying Chen,Lin He,Loke Kun Tan,Aravind Padyana,Vincent Cheng-Hsun Yang,Gregory Unruh,Jackie Koon Lun Wong,Bryan Juo-Jung Hung,Massimo Brandolini,Maco Sha-Ting Lin,Xi Chen,Yen Ding,Yen-Jen Ko,Young J. Shin,Ada Hing T. Hung,Binning Chen,Cynthia Dang,Deepak Lakshminarasimhan,Iris Hong Liu,Jerry Lin,Kowen Lai,Larry Wassermann,Ayaskant Shrivastava,Chi-Ming Hsiao,Chun-Sheng Huang,Jianlong Chen,Lakshminarasimhan Krishnan,Ning-Yi Wang,Pin-En Su,Tianwei Li,Wei-Ta Shih,Yau-Cheng Yang,Peter Cangiane,Randall Perlow,William Ngai, Hanson Hung-Sen Huang,James Y. C. Chang,Xicheng Jiang,Ardie Venes,Ramon Ray Gomez

IEEE Journal of Solid-State Circuits（2016）

Cited 27|Views85
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Abstract
A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalit...
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Key words
Receivers,Cable TV,Gain,Phase locked loops,Bandwidth,Digital signal processing,CMOS integrated circuits
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