A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS

IEEE Journal of Solid-State Circuits(2015)

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摘要
This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-app...
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关键词
Calibration,Clocks,Timing,Signal to noise ratio,Receivers,Switches
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