Design and synthesis of reconfigurable control-flow structures for CGRA

Coarse-Grained Reconfigurable Architectures (CGRA) promise both low power and high performance coupled with flexibility, however automatic mapping of applications to such platforms remains a great research challenge. Efficient manual mapping of the data-centric kernels of applications yields great results, however these contain internally control-flow specific tasks, which introduce mapping irregularities and execution inefficiencies on CGRAs. In this paper, we explore analysis, design and synthesis of reconfigurable structures for efficient application-specific control-flow processing, aiming to develop a methodology to design reconfigurable control-flow acceleration modules. Such modules can be coupled with generic CGRAs, off-loading execution of irregular and ill-suited sequential control-flow subroutines, enabling the CGRA to exploit a clean, regular data-flow centric mapping. Considering different architectural paradigms, we design and compare a functional array-based design, a VLIW-style design and an automatically generated design based on graph theoretic concepts against the ASIC implementation of the control flow operations for several kernels of the linear algebra domain. Such reconfigurable control-flow specific accelerators are a first step towards automating CGRA-based accelerator design and application mapping from high-level descriptions.