A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)(2015)

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Designing applications for heterogeneous systems, like Multiprocessor System-on-Chips (MPSoCs) based on Field Programmable Gate Arrays (FPGAs) is a complex task. In order to exploit all the capabilities of these systems, such as Partial Dynamic Reconfiguration (PDR) and hardware acceleration, the designer still has to develop large parts of the system unassisted, establishing the design choices (i.e., whether to assign a task of the application on a hardware region of the FPGA or a general purpose processor of the SoC) mostly on his/her experience. In this paper we present a Mixed-Integer Linear Programming (MILP) formulation for mapping and scheduling of applications on heterogeneous and reconfigurable devices taking into account PDR, module reuse and configuration prefetching. Starting from a target architecture and a description of the application in terms of tasks and data dependencies, the proposed formulation allows the designer to optimize a linear combination of different metrics such as execution time, peak power and energy consumption.
multiobjective reconfiguration-aware scheduler,FPGA-based heterogeneous architecture,heterogeneous system,multiprocessor system-on-chip,MPSoC,field programmable gate array,partial dynamic reconfiguration,PDR,hardware acceleration,design choice,general purpose processor,mixed-integer linear programming formulation,MILP formulation,heterogeneous device,reconfigurable device,module reuse,configuration prefetching,target architecture,data dependency,linear combination,execution time,peak power,energy consumption
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