Statistical fault injection for impact-evaluation of timing errors on application performance

DAC, pp. 13:1-13:6, 2016.

Cited by: 5|Views10
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Abstract:

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circuit structure, hence allowing for a significantly more detailed characterization of ...More

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