Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs
IEEE Computer Society Annual Symposium on VLSI, pp. 619-624, 2016.
State-of-the-art techniques for enhancing system-level reliability for SoCs include both design-time and run-time strategies, such as task mapping and reliable communication network design. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication network design involves the reliability eva...More
Full Text (Upload PDF)
PPT (Upload PPT)