Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

Alessandro Littarru
Alessandro Littarru
Emmanuel Ikechukwu Ugwu
Emmanuel Ikechukwu Ugwu
Shazia Kanwal
Shazia Kanwal

IEEE Computer Society Annual Symposium on VLSI, pp. 619-624, 2016.

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Abstract:

State-of-the-art techniques for enhancing system-level reliability for SoCs include both design-time and run-time strategies, such as task mapping and reliable communication network design. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication network design involves the reliability eva...More

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