Power-aware virtual machine mapping in the data-center-on-a-chip paradigm
ICCD, pp. 241-248, 2016.
It is projected that hundreds of cores can be integrated into a chip at the sub-20nm technology nodes. However, some challenges exist in the many-core architecture such as maintaining memory coherence, underutilized parallelism, and increased inter-core communication delay. This work proposes the data-center-on-a-chip (DCoC) paradigm empl...More
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