A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.


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Iterative Stencil Loops (ISLs) are a specific class of algorithms of great importance for their substantial presence in a lot of industrial and scientific computing applications, such as in numerical methods for solving partial differential equation -- e.g. reverse time migration and heat distribution simulation --- or in cellular automata --- used for instance for random number generation and error correction. In this work, we propose a hardware acceleration methodology based on the polyhedral model and implement the related framework to automatically accelerate ISLs on a multi-FPGA system. The experimental evaluation shows that the throughput obtained by our solution scales linearly with the amount of resources used on the FPGAs, the power efficiency increases proportionally to the amount of instantiated computation, and outperforms the power efficiency figure of state of the art ISL implementations running on an Intel Xeon CPU by at most 10x. A key aspect of this approach is also that no knowledge of the underlying architecture is requested to the application designer, as no code refactoring is needed to make the application suitable to be processed by our framework.
FPGAs,Dataflow Architectures,Polyhedral Model,Power Efficiency
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