Configurable FPGA architecture for hardware-software merge sorting

Sorting represents one of the most important operations in data center applications. In this paper, we propose a hardware-software FPGA accelerated based solution for very large data set merge sorting. The accelerator is using a FIFO based approach for sorting. The main contributions of the proposed solution are: (i) configurable FIFO buffers in order to address the variable size of the pre-sorted arrays in the merge sorting algorithm, and (ii) FIFO buffer size tailored for reduced memory usage of the software component. The proposed solution has been implemented on Xilinx Zynq platform. We present FPGA synthesis results for different configurations of FIFO depths and number of FIFO based sorters.