Layered T Methodology In Qca Nand/Nor Based Circuit Designing Approach

Quantum Cellular Automata now has several deduction methodologies none of which explores universal NAND/NOR based design in Boolean reduction techniques. As Boolean laws reveal the intuitive NAND and NOR based reductions, higher cell requirement for majority function can be avoided if NAND/NOR based methodology is used. This work proposes Layered T Gate (LT Gate) which works on the basis of universal NAND and NOR logic. Layered T gate requires algorithms to implement digital designs especially if standard functions are to be considered. Layered T Gate is also used to implement 2X1 multiplexer as primitive who shows 37.3% reduction in area requirement compared to the latest design.