Towards Ideal Hop Counts in Interconnection Networks with Arbitrary Size

Designing low-latency network topologies of switches is a key objective for next-generation parallel computing platforms. Low latency is preconditioned on low hop counts, but existing network topologies have hop counts much larger than theoretical lower bounds. The degree diameter problem (DDP) has been studied for decades and consists in generating the largest possible graph given degree and diameter constraints, striving to approach theoretical upper bounds. To generate network topologies with low hop counts we propose using best known DDP solutions as starting points for generating topologies of arbitrary size. Using discrete-event simulation, we quantify the performance of representative parallel applications when executed on our proposed topologies, on previously proposed fully random topologies, and on a classical non-random topology.