A 1.2 V 2.64 Gs/S 8 Bit 39 Mw Skew-Tolerant Time-Interleaved Sar Adc In 40 Nm Digital Lp Cmos For 60 Ghz Wlan

A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a "correct-by-construction," timing-calibration-free global bottom-plate sampling scheme. The ADC achieves a sampling rate of 2.64 GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40 nm LP CMOS design dissipates 39 mW from 1.2 V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44 dB EVM at sensitivity with a QAM16 signal.