Serial Arithmetic Strategies for Improving FPGA Throughput

ACM Trans. Embedded Comput. Syst., Volume 16, Issue 3, 2017, Pages 84:1-84:25.

Cited by: 0|Bibtex|Views1|DOI:https://doi.org/10.1145/2996459
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Abstract:

Serial arithmetic has been shown to offer attractive advantages in area for field-programmable gate array (FPGA) datapaths but suffers from a significant reduction in throughput compared to traditional bit-parallel designs. In this work, we perform a performance and trade-off analysis that counterintuitively shows that, despite the decrea...More

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