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Self-Adaptive Timing Repair

IEEE design & test(2017)

Cited 1|Views19
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Abstract
This article describes a method to continuously monitor paths delays in an operational FPGA design and to improve slow paths by incremental partial reconfiguration. Since online delay measuring is more accurate than design time estimation, this approach allows to balance delays which can be used to improve performance or reduce power consumption. In addition, it counteracts aging effects and prolo...
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Key words
Logic gates,Delays,Field programmable gate arrays,System-on-chip,Transistors,Maintenance engineering,Semiconductor device measurement
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