A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

Aniruddha Shastri
Aniruddha Shastri

Int. J. Reconfig. Comp., Volume 2017, 2017, Pages 5419767:1-5419767:17.

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Abstract:

Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing. Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Furthermore, this overhead i...More

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