An efficient successive cancellation polar decoder based on new folding approaches

In this paper, an efficient successive cancellation (SC) polar decoder based on new folding approaches is proposed. The main approach of this paper is called k-level decomposition with 2 ^p sub-decoders. Adjusting k and p, the derived architecture can have a very low processing complexity with proper combinations of decomposition method and folding technique. Compared to state-of-the-art designs, hardware utilization ratio (HUR) of processing elements can be drastically improved with small latency overhead. Meanwhile, the memory complexity remains similar. Furthermore, decomposition and folding operations can also be applied to a family of hybrid polar decoders. To validate efficiency of these approaches, two folded SC decoders with N = 64 and 1024 respectively are implemented with Altera Stratix V FPGA. These two demos require only 68.3% and 39.1% ALMs, compared to the non-decomposed SC decoder.