A 126mw 56gb/S Nrz Wireline Transceiver For Synchronous Short-Reach Applications In 16nm Finfet

The industry has recently proposed standards for synchronous high-speed interfaces targeting chip-to-chip communication across a very short PCB trace [1]. Figure 16.7.1 shows an example of such an interface. Eight 56Gb/s NRZ lanes provide a total of 448Gb/s aggregate bandwidth in each direction. The channel insertion loss and propagation delay varies from lane to lane, with a maximum insertion loss of 8dB at 28GHz from BGA to BGA. The routing inside the two packages adds an additional 3dB insertion loss at 28GHz. Taking advantage of the relatively low channel loss, the interface is expected to adopt simple transmitter/receiver circuits with low power consumption. However, a per-lane deskewing scheme is still required due to the propagation delay variations between lanes.