Challenges in Large FPGA-based Logic Emulation Systems

ISPD, pp. 26-33, 2018.

Cited by: 6|Bibtex|Views24|Links
EI

Abstract:

Functional verification is an important aspect of electronic design automation. Traditionally, simulation at the register transfer-level has been the mainstream functional verification approach. Formal verification and various static analysis checkers have been used to complement specific corners of logic simulation. However, as the size ...More

Code:

Data:

Your rating :
0

 

Tags
Comments